发明名称 Testing a device under test by sampling its clock and data signal
摘要 There is provided a method that includes (a) sampling a data signal and a clock signal by applying strobes for obtaining a corresponding bit values each for the data signal and for the clock signal, each of the strobes having a different phase offset with respect to a tester clock signal, (b) deriving first comparison results for the bit values of the data signal by comparing the bit values of the data signal each with an expected data bit value of expected data, (c) deriving second comparison results for the bit values of the clock signal by comparing the bit values of the clock signal each with an expected clock bit value, (d) deriving for the strobes combined comparison results by applying logical operations each on pairs of corresponding first and second comparison results, and (e) deriving a test result based on the combined comparison results.
申请公布号 US7260493(B2) 申请公布日期 2007.08.21
申请号 US20060353662 申请日期 2006.02.14
申请人 VERIGY (SINGAPORE) PTE. LTD. 发明人 LAQUAI BERND;MOHR JOERG-WALTER
分类号 G06F19/00 主分类号 G06F19/00
代理机构 代理人
主权项
地址