| 摘要 |
It is made possible to control RAMs of a plurality of kinds differing in control system by using a single memory controller (LSI). A memory control circuit having an LSI configuration receives a RAM access request signal, which does not depend on a classification of a RAM device, from a high rank control unit such as a CPU (not shown), and transmits a RAM control signal & data group to a subordinate RAM device to control it. Upon receiving the RAM access request signal, the memory access RAM busy management circuit generates RAM control command & data suitable for the currently connected RAM device, and transmits it to the memory access common control circuit. Upon receiving the RAM control command & data, the memory access common control circuit generates RAM control signal & data group and transmits it to the RAM device.
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