发明名称 Static CMOS logic level shift circuit with a low logic input count high switching speed and low power dissipation
摘要 A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting relatively low impedance and low capacitance. Long channel transistors are arranged to receive a first voltage from the short channel transistors and provide an output voltage and an inverted output voltage, which are also employed to control the short channel transistors. A first switching transistor of the switching circuit enables the short channel and the long channel circuits to provide the output voltage based on a low input voltage and a logic input voltage. A second switching transistor enables the same circuits to provide the inverted output voltage based on the logic input voltage.
申请公布号 US7259610(B1) 申请公布日期 2007.08.21
申请号 US20040949111 申请日期 2004.09.24
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 BELL MARSHALL J.;KOZISEK JAMES R.
分类号 H03L5/00 主分类号 H03L5/00
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