| 摘要 |
A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T 1 and T 2 orthogonally to opposed lateral end faces out of lateral end faces X 1 , X 2 , Y 1 , and Y 2 that section the cell in a plane direction. Contact surfaces of the electrode surfaces T 1 and T 2 with the lateral end faces are second connection terminals T 12 and T 22 . For longitudinal pathways, first and second via contact layers V 1 and V 2 are connected. The first via contact layer V 1 interconnects the wiring layers Ma and Mb. The second via contact layer V 2 is connected to a wiring layer located outside beyond an upper or lower end face Z 2 , Z 1 . The second via contact layer V 2 is connected to a first connection terminal T 11 , T 21 located on the upper or lower end faces Z 2 , Z 1 . The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.
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