发明名称 CACHE OBSERVATION SYSTEM, ANALYSIS METHOD OF PROCESSOR, AND CACHE MEMORY
摘要 PROBLEM TO BE SOLVED: To solve a problem that difference of transfer speed with the outside of a chip becomes large associated with the increase in processor speed, and the transfer speed is not enough at the trace terminal for outputting trace information by clock cycle of the processor, resulting in unsuccessful data acquisition. SOLUTION: A cache failure judgement means e1 judges cache failure at the access to a cache memory 3 divided into a plurality of cache entries. An entry domain judgement means e2 judges that to which entry domain of the cache memory 3 the cache access is accessing by using a part of index that is a part of address to select arbitrary cache line in the cache memory 3. A cache failure frequency calculation means e10 calculates the frequency of the cache failure by the cache failure judgement means e1 for every cache entry domains by the entry domain judgement means e2, and acquires data effective for optimization of program. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007206806(A) 申请公布日期 2007.08.16
申请号 JP20060022470 申请日期 2006.01.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUDA GENICHIRO
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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