发明名称 AUTOMATIC DETECTION OF MICRO-TILE ENABLED MEMORY
摘要 In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the memory channel. A read cache line is read from memory in the memory channel at the starting address. The bit patterns of the read cache line and the write cache line are compared. If in the comparison it is determined that the bit pattern of the read cache line differs from the write cache line, then micro-tile memory access is enabled into each memory integrated circuit on memory modules in the memory channel. If in the comparison it is determined that the bit pattern of the read cache line is the same as the bit pattern of the write cache line, then micro- tile memory access is not supported and cannot be enabled in each memory integrated circuit on memory modules in the memory channel.
申请公布号 WO2007005551(A3) 申请公布日期 2007.08.16
申请号 WO2006US25460 申请日期 2006.06.28
申请人 INTEL CORPORATION;GABEL, DOUGLAS;AKIYAMA, JAMES 发明人 GABEL, DOUGLAS;AKIYAMA, JAMES
分类号 G06F13/16 主分类号 G06F13/16
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