| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technology improved for erasing contents of a float gate memory cell, capable of maintaining an erasing speed constant during an erasing operation. <P>SOLUTION: A circuit for applying a negative voltage (NVPP) to the control gate of a float gate memory cell 10 and a positive voltage to a source or a drain includes a positive voltage source for supplying a positive voltage to the source 13 of the cell, and a negative voltage source for applying a negative voltage to a control gate in response to a supplied voltage. The circuit includes a voltage adjuster 21 connected to the positive and negative voltage sources to maintain a negative voltage at a certain level in response to a source voltage. The adjuster maintains the negative voltage in response to the source voltage so that an electric field substantially stays constant within the value range of the source voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT |
