发明名称 PACKET PROCESSING APPARATUS AND METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To solve a problem that it is difficult to perform complicated processing on a packet since a processing time allocated to processing one packet is limited in a conventional packet processing apparatus using a dataflow type network processor. <P>SOLUTION: A packet processing apparatus is configured to perform distributed processing on packet processing using a packet processing engine and a search engine, a device internal header containing a search key is appended to each of packets received through a main line, and such a device internal header is added to data. Even when one time of packet processing time is limited, complicated processing can be performed on packets by packet loop processing adding, step by step, processing to the packets while iteratively delivering the data between the packet processing engine and the search engine. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007208963(A) 申请公布日期 2007.08.16
申请号 JP20060334489 申请日期 2006.12.12
申请人 FUJITSU LTD 发明人 OKADA TETSUYA
分类号 H04L12/701;H04L12/741;H04L12/775;H04L12/947 主分类号 H04L12/701
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