MULTI-CORE ARCHITECTURE WITH HARDWARE MESSAGING

摘要

Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits (200) include processors having dedicated messaging hardware (210) that enable processor cores (212) to minimize interrupt activity related to inter- core communications. The messaging hardware receives (604) and parses (610) any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.