发明名称 IMPURITY ANALYSIS METHOD, AND IMPURITY ANALYSIS JIG OF SEMICONDUCTOR SUBSTRATE
摘要 PROBLEM TO BE SOLVED: To provide an impurity analysis method and an impurity analysis jig of a semiconductor substrate having a sufficient accuracy. SOLUTION: A main surface of a semiconductor substrate is masked with a protective plate having an opening in a central part, the etching liquid is spread in the opening of the protective plate, and the method comprises: a first step (S01 to S04) of etching a surface layer of the semiconductor substrate; a second step (S05 to S06) of analyzing impurity in the surface layer of the semiconductor substrate; and a third step (S07 to S10) of sandwiching the etching liquid between gaps and etching a non-etched area of the surface layer of the semiconductor substrate, wherein the first to third steps are repeated for a prescribed number of times (S11). Contamination from the non-etched area of the surface layer of the semiconductor substrate is prevented to perform impurity analysis. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007208198(A) 申请公布日期 2007.08.16
申请号 JP20060028643 申请日期 2006.02.06
申请人 TOSHIBA CORP 发明人 MIZUNO AYAKO;UOZUMI NOBUHIRO
分类号 H01L21/66 主分类号 H01L21/66
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