| 摘要 |
<p>The device has standard logic gates e.g. NOR logic gates, provided with complementary reading/writing terminals (Q, Qb), and a bistable circuit supplied by a supply voltage (Vdd). A control input (RS) is connected to the circuit, where the input acquires a logic state that controls a pre-loading phase of the circuit independent of a rising phase of the supply voltage. The control input acquires another logic state that controls the establishment of a memory bit and its complement at the level of the reading/writing terminals.</p> |
