发明名称 Encoding viterbi error states into single chip sequences
摘要 A technique for receiving an error state in a single chip sequence in a wireless communications network is disclosed. The error state may comprise a Viterbi error state. The error state may be identified as a target code encoded in the single chip sequence, the target code comprising either a code or the complement of the code. The code may comprise a PN-Code. The error state may be identified using a previous mapping of error states from a set of error states to a group of codes, the group of codes comprising a plurality of codes and their complements. The error states in the set of error states in the previous mapping may be uniquely mapped to plurality of codes and their complements in the group of codes.
申请公布号 US7257147(B1) 申请公布日期 2007.08.14
申请号 US20020324990 申请日期 2002.12.20
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 MACK ROBERT W. E.;BEARD PAUL F.
分类号 H04B1/00 主分类号 H04B1/00
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