| 摘要 |
A burn-in sorting method is provided to reduce time for sorting a DC test error IC(Integrated Circuit) by employing a process for sorting an IC that is abnormal in a DC test. A first IC being burn-in tested is received in a burn-in board. The burn-in board receiving the first IC is positioned on a board table(S10). A second IC is picked from a loading tray to be received in a DC test buffer(S20). A DC test is performed on the second IC received in the DC test buffer(S30). The first IC received in the burn-in board is picked to be received in an unloading buffer(S40). All of second ICs being DC tested are picked to be received in vacancy sockets of the burn-in board(S50). A second IC having a DC error among the second ICs received in the burn-in board is received in a DC error tray(S70). The first IC being received in the unloading buffer is received in the unloading tray or at least one sorting tray according to a burn-in grade(S60).
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