发明名称 Semiconductor memory having twisted bit line architecture
摘要 A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.
申请公布号 US7257011(B2) 申请公布日期 2007.08.14
申请号 US20050258922 申请日期 2005.10.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MIYAKAWA TADASHI;TAKASHIMA DAISABURO
分类号 G11C5/08;G11C5/06 主分类号 G11C5/08
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