发明名称 |
Method and system for hardware accelerated verification of digital circuit design and its testbench |
摘要 |
A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.
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申请公布号 |
US7257802(B2) |
申请公布日期 |
2007.08.14 |
申请号 |
US20040972361 |
申请日期 |
2004.10.26 |
申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
DAW JYOTIRMOY;GUPTA SANJAY;KRISHNAMURTHY SURESH |
分类号 |
G06F17/50;G01R31/3183 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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