发明名称 |
Method for integrally checking chip and package substrate layouts for errors |
摘要 |
A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.
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申请公布号 |
US7257784(B2) |
申请公布日期 |
2007.08.14 |
申请号 |
US20050089108 |
申请日期 |
2005.03.24 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHENG CHIA-LIN;WU EJ;CHANG SHIH-CHENG;CHEN KUO-YIN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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