Processor e.g. microcontroller, has debugging interface with internal registers accessible to emulator, and selection circuit for selecting registers based on reference provided by CPU

摘要

#CMT# #/CMT# The processor has a CPU, and a debugging interface (OCE) connected to an external emulator (H) for debugging a program executed by the processor. The interface has internal registers (ER0-ERn) accessible to the emulator, and a selection circuit for selecting registers based on a reference provided by the CPU. A data bus transfers data between the selected register and a data field accessible by the CPU. #CMT# : #/CMT# An independent claim is also included for a method for accessing internal resources by a CPU of a processor. #CMT#USE : #/CMT# Processor e.g. microprocessor or microcontroller. #CMT#ADVANTAGE : #/CMT# The processor renders the internal registers of the debugging interface accessible to the CPU by reading and writing, when the emulator is not connected to the debugging interface, without loading an access bus of the processor and without increasing the number of components. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows an architecture of a processor. COR : Register ER0-ERn : Internal registers H : External emulator JRG : Bus interface unit OCE : Debugging interface #CMT#INDUSTRIAL STANDARDS : #/CMT# The internal registers are accessible via a joint test access group type external port conforming to IEEE 1149.1 standard.