| 摘要 |
PROBLEM TO BE SOLVED: To efficiently discriminate the normal/defective state of a memory to be tested in which latency can be changed. SOLUTION: The test device is provided with a pattern generator successively generating a control command supplied to the memory to be tested, an address, and a test pattern including write-in data written in the memory to be tested and an expected value of read-out data read out of the memory to be tested based on predetermined algorithm, a signal input/output part supplying the control command, the address, and the write-in data to the memory to be tested, and receiving read-out data outputted by the memory to be tested, a discriminating part comparing the read-out data and an expected value and discriminating the quality of the read-out data, a detecting part detecting whether the test pattern generated by the pattern generator is a latency setting command or not, and a setting part setting write-in latency and read-out latency of the signal input/output part to a value in accordance with the latency setting command in the write-in of data for the memory to be tested when the detecting part detects the latency setting command. COPYRIGHT: (C)2007,JPO&INPIT
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