发明名称 BUFFER MEMORY TEST CIRCUIT AND BUFFER MEMORY TEST METHOD
摘要 PROBLEM TO BE SOLVED: To solve the following problem of a buffer memory test by a test program: because an access time of a ROM storing the test program is slow, a test time of a buffer memory test by the test program is lengthened as capacity of a buffer memory is increased to slow a start-up time of a communication device. SOLUTION: This buffer memory test circuit has: a test pattern generation part 110 generating a test pattern for testing normality of the buffer memory 300; a test pattern collation part 111 generating a collation pattern of the same pattern as the test pattern, and comparing the collation pattern and a read pattern obtained by reading the test pattern written in the buffer memory 300 to collate whether two sides accord or not; and a test control register 109 controlling them. By incorporating the buffer memory test circuit in a communication processing integrated circuit 100, the test time is reduced. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007200073(A) 申请公布日期 2007.08.09
申请号 JP20060018583 申请日期 2006.01.27
申请人 OKI ELECTRIC IND CO LTD;OKI COMTEC LTD 发明人 SAITO IKUO
分类号 G06F12/16;G01R31/28 主分类号 G06F12/16
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