| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the scale of an operation hardware in an image encoder and an image decoder. <P>SOLUTION: The image encoder and image decoder based upon H.264/AVC is provided with an adder array part 114 capable of switching the configuration of a computing unit required for a generating operation of 1/4 precision predicted pixel of luminance 16×16 pixel blocks in prediction processing between frames and a generation operation of predicted pixel blocks in prediction processing in a frame corresponding to prediction modes, and the adder array part 114 is shared by the prediction processing in the frame and the prediction processing between frames. <P>COPYRIGHT: (C)2007,JPO&INPIT |
