发明名称 DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To detect delay deterioration after laying out due to a netlist correction in an early stage. SOLUTION: The number of steps and the path length of a path to be extracted from a netlist are obtained for a uncorrected netlist (trial netlist) and corrected netlist (evaluation target netlist), and delay difficulty showing the difficulty of delay improvement is calculated on the basis of the obtained number of steps and path length. Then, delay increase and a delay value in the real load delay verification of the evaluation target netlist are predicted on the basis of a difference between the delay difficulty of the path in the trial netlist and the delay difficulty of the path in the evaluation target netlist and the delay value in the real load delay verification of the trial netlist. The netlist of the trial netlist and layout information in the case of initial layout and the delay value in the real load delay verification are applied so that it is possible to detect delay deterioration due to the changes of the number of steps, and the possibility of the delay deterioration due to the change of the path length in the stage of the initial layout of the evaluation target netlist. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007199951(A) 申请公布日期 2007.08.09
申请号 JP20060016822 申请日期 2006.01.25
申请人 NEC CORP 发明人 UCHIDA RISAKO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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