| 摘要 |
A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction, an interlock generation circuit for generating an interlock until a pipeline of a loop instruction is completed so as to suspend a pipeline process of the loop end instruction, and a loop end evaluation circuit for setting the program counter to the loop start address according to a result of a comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.
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