| 摘要 |
A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.
|
