| 摘要 |
A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.
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