发明名称 TESTING PROCEDURE FOR INTEGRATED CIRCUITS
摘要 PROBLEM TO BE SOLVED: To provide a device, as well as, a process evaluating the occurrence of failures or the possibility of the failures in integrated circuits. SOLUTION: The present invention is of process for evaluating the occurrence of failures or of the possibility of the failures in integrated circuits. The process includes formation of electrically conductive domain, such as a runner around a substrate or a dice. The electrically conductive domain is prepared at one or a plurality of different metallization layers within an integrated circuit. The electrically conductive domain is coupled to one or a plurality of bonding pads. The dice is detected by measuring the resistance, electrical conductivity, crosstalks, or other electrical characteristics on the electrically conductive region through the bonding pads. The detection can be utilized to predict whether there is failure of a runner generated within the integrated circuit or there is a possibility of failures. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007199082(A) 申请公布日期 2007.08.09
申请号 JP20070063290 申请日期 2007.03.13
申请人 AGERE SYSTEMS GUARDIAN CORP 发明人 VIVIAN RAYAN;THOMAS HERBERT SCHILLING
分类号 G01R31/26;G01R31/28;G01R31/02;H01L21/66;H01L21/822;H01L23/544;H01L27/04 主分类号 G01R31/26
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