| 摘要 |
PROBLEM TO BE SOLVED: To provide a test mode semiconductor memory device in which individual reset can be performed. SOLUTION: The device is provided with a control signal generator for combining command signals applied from an external portion to generate a test signal, a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset, a test logic portion for storing and then outputting the mode setting in response to the test signal signal, a set/reset master signal generator to which the first set/reset signal and the test signal are applied and which outputs the set/reset master signal for commonly controlling the test mode of internal blocks of the semiconductor memory device, and a test control signal generator for combining the mode setting signal output from the test logic portion to generate a plurality of control signals and generating the set/reset master signal as a plurality of test control signals in response to the plurality of control signals. COPYRIGHT: (C)2007,JPO&INPIT
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