发明名称 PROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To suppress worsening of a branch penalty due to an increased number of instruction execution cycles of a main processor matched to the number of instruction execution cycles of a coprocessor. SOLUTION: If the number of instruction execution cycles of an extended instruction to be executed by a coprocessor 20 is larger than the number of instruction execution cycles of a basic instruction to be executed by a main processor 10, a processor system 1 stops pipeline processing for the subsequent instruction acquired after the extended instruction, at least for a period corresponding to the difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction, when the extended instruction is executed by the coprocessor 20. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007200180(A) 申请公布日期 2007.08.09
申请号 JP20060020332 申请日期 2006.01.30
申请人 NEC ELECTRONICS CORP 发明人 KASHIWAGI SHINJI
分类号 G06F9/38 主分类号 G06F9/38
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