| 摘要 |
A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four "slots," each including four bytes, and locates scalar data in "preferred slots" to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.
|
