发明名称 Topologie zur Verfügungstellung von Taktsignalen an mehrere Schaltungseinheiten auf einem Schaltungsmodul
摘要 <p>A circuit module has a circuit board (50a), multiple circuit units (20a to 52i) on the circuit board (50a) and at least one clock input (12a) on the circuit board (50a) for receiving an external clock signal. The circuit module has a first PLL unit (60) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit (62) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units. <IMAGE></p>
申请公布号 DE60308637(T2) 申请公布日期 2007.08.09
申请号 DE2003608637T 申请日期 2003.03.11
申请人 INFINEON TECHNOLOGIES AG 发明人 KUZMENKA, MAKSIM;CHENNUPATI, SIVA RAGHURAM;BACHA, ABDALLAH;MUFF, SIMON
分类号 G06F1/10;G11C7/22;G11C11/4076;H03K5/15;H03L7/06;H03L7/07;H05K1/02;H05K1/18 主分类号 G06F1/10
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