| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a reset signal-generating circuit which switches reset signal generation timing between synchronization and asynchronization, in accordance with an operational state, to generate reset signals. <P>SOLUTION: An operation detection circuit 21 detects the operation of a CPU and outputs an operation detection signal OC. A signal control circuit 22 responds to a system reset signal RSTX based on the operation detection signal OC and outputs a reset signal C_RST in synchronization or asynchronization with an internal clock signal CLK. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
