| 摘要 |
PROBLEM TO BE SOLVED: To shorten a time until a dutycycle of a demodulated signal is settled to a reference dutycycle. SOLUTION: While a switch circuit 21 is changed to an averaging circuit 20 side, a comparator 14 compares a signal Sd detected by a detection circuit 15 and an average value Vavg of the averaging circuit 20, and outputs a demodulated signal So. A counter 25 counts clock numbers of N1 and N2 in each interval of H and L of the signal So. A regulator 27 calculates the dutycycle of the signal So based on the clock numbers N1 and N2, and sets a reference instruction value Dr so that the dutycycle approximates to the reference dutycycle (50%). Afterward, the switch circuit 21 is switched to a regulator circuit 26 side, and regulation processing is repeated by a sequential search method or a binary search method. COPYRIGHT: (C)2007,JPO&INPIT
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