| 摘要 |
<P>PROBLEM TO BE SOLVED: To lessen the impact of heating between adjoining memory cells. <P>SOLUTION: A memory cell comprises a heater element 12 which generates heat upon conduction, a chalcogenide layer 10 in which phase transformation takes place upon heating, and transistors 16 and 18 for driving them. A bit line BL is arranged to extend in a predetermined direction and connected electrically with the memory cell. A word line WL(WU) is arranged to extend in the direction intersecting the bit line perpendicularly and connected electrically with the memory cell. A first cell array where the memory cells are arranged at positions A1, A2, A3, ..., at a constant interval 2d in the extending direction of the bit line BL, by d and a second cell array where the memory cells are arranged at positions B1, B2, B3, ..., determined by shifting the first cell array in the extending direction of the bit line BL by d are provided. The first and second cell arrays are arranged, at a constant interval d, in the extending direction of the word line WL(WU) such that the memory cells exist checkerwise. <P>COPYRIGHT: (C)2007,JPO&INPIT |
