| 摘要 |
A nonvolatile semiconductor memory device is provided to micro-machine a transistor of a sub decode device without increasing a parasitic MOS leak current. A memory cell array has a plurality of memory cells arranged in a matrix. A plurality of word lines is arranged in correspondence to each memory cell row, and is connected to each corresponding row memory cell. A sub decoder circuit includes a sub decode device arranged in correspondence to each word line, and sets the voltage of a word line according to a part of a source signal and a part of a gate signal. A block decode circuit generates the source signal according to an address signal. A gate decode circuit generates the gate signal according to an address signal.
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