| 发明名称 |
COARSE DELAY TUNER CIRCUITS WITH EDGE SUPPRESSORS IN DELAY LOCKED LOOPS |
| 摘要 |
<p>The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.</p> |
| 申请公布号 |
EP1573912(B1) |
申请公布日期 |
2007.08.08 |
| 申请号 |
EP20030775714 |
申请日期 |
2003.12.08 |
| 申请人 |
NXP B.V. |
发明人 |
EASWARAN, SRI, NAVANEETHAKRISHNAN |
| 分类号 |
H03K5/13;H03K5/1252;H03L7/00;H03L7/081;H03L7/10 |
主分类号 |
H03K5/13 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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