发明名称 Standard cell library having cell drive strengths selected according to delay
摘要 A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength.
申请公布号 US7254802(B2) 申请公布日期 2007.08.07
申请号 US20040856345 申请日期 2004.05.27
申请人 VERISILICON HOLDINGS, CO. LTD. 发明人 ZHANG XIAONAN;WANG MICHAEL XIAONAN
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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