发明名称 Write transaction interleaving
摘要 A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.
申请公布号 US7254658(B2) 申请公布日期 2007.08.07
申请号 US20040862872 申请日期 2004.06.08
申请人 ARM LIMITED 发明人 HARRIS ANTONY JOHN;MATHEWSON BRUCE JAMES
分类号 G06F13/00 主分类号 G06F13/00
代理机构 代理人
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