发明名称 Dual damascene process
摘要 A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.
申请公布号 US7253112(B2) 申请公布日期 2007.08.07
申请号 US20040915633 申请日期 2004.08.10
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 HO BANG-CHIEN;CHEN JIAN-HONG;WU TSANG-JIUH;LIN LI-TE;CHAO LI-CHIH;LIN HUA-TAI;LU SHYUE-SHENG
分类号 H01L21/311;H01L21/768 主分类号 H01L21/311
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