发明名称 THE DESIGN OF MULTI-LAYER PASSIVE ELEMENT USING EMBEDED GROUND PLATE AND EFFECT OF PARACITIC CAPACITANCE.
摘要 A multi-layer passive element having an embedded ground plate is provided to reduce a size of the multi-layer passive element by adjusting a parasitic capacitance component between the ground plate and a signal conductor. A laminated passive circuit is made by using an LTCC(Low Temperature Cofired Ceramic) technology. Plural passive elements, such as distributed elements, are formed on the passive circuit. Parasitic capacitance is generated between the passive elements. The parasitic capacitance formed between a ground plate and a signal conductor is controlled. A distance between the ground plate and the signal conductor is increased, so that the parasitic capacitance is reduced. The parasitic capacitance between the ground plate and the signal conductor is adjusted without increasing an overall thickness of the passive circuit.
申请公布号 KR20070079473(A) 申请公布日期 2007.08.07
申请号 KR20060010175 申请日期 2006.02.02
申请人 KIM, YU SEON 发明人 LIM, YEONG SEOG;KIM, YU SEON
分类号 H01G4/33 主分类号 H01G4/33
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