| 摘要 |
A data input circuit and method of a semiconductor memory device are provided to reduce power consumption by outputting a row enable signal or a write enable signal selectively according to frequency of a clock as a buffer enable signal when the length of write latency is shorter than a reference length. A write latency control unit(10) generates a buffer enable signal from a row active command, a row precharge command, a write command, a burst end signal and a plurality of write latency signals according to the control of a low frequency operation mode signal. A data input buffer(20) buffers input data in correspondence to the input of the buffer enable signal. The low frequency operation mode signal is a DLL(Delay Locked Loop) off signal.
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