TEST MODE OPERATING CIRCUIT OF SEMICONDUCTOR MEMORY

摘要

A test mode operating circuit of a semiconductor memory is provided to prevent a test mode operation error due to glitch by using a test mode enable signal. A glitch prevention part(300) receives a test mode enable signal and a test mode signal as inputs. A signal input part(400) receives an operation signal and a test mode input signal output from the glitch prevention part. A latch part(500) latches a signal output from the signal input part. The glitch prevention part includes a NAND gate(ND1) receiving the test mode enable signal and the test mode signal and an inverter unit(IV41) inverting a signal output from the NAND gate.