| 摘要 |
An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs. |
