| 摘要 |
<p>A test device comprising a storage section for storing the count for adjusting the phase of a sampling clock indicating the timing at which the output signal outputted from a DUT is acquired, a clock generating section for generating the sampling clock indicating the timing at which the output signal is acquired according to the offset corresponding to the reference clock and the count, a first delay section for outputting a first delay clock having the same frequency as the sampling clock and a predetermined phase difference according to the reference clock and the offset, a phase detecting section for detecting the phase deference between the point of variation of the output signal and the first delay clock and varying the count so that the phase difference may decreases, a timing comparing section for acquiring the output signal at a variation timing of the sampling clock, and a judging section for judging the acceptance/rejection by comparing the acquired output signal and the expectation.</p> |
