| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve speed of cache read in a semiconductor memory device. <P>SOLUTION: A primary data cache PDC is connected to a common signal line and a secondary data cache SDC is connected to an input/output data line. When data of the secondary data cache SDC is output to the input/output data line, speed of cache read is increased by discriminating data of a flag cell using the common signal line. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
