发明名称 |
NANOWIRE TUNNELING TRANSISTOR |
摘要 |
<p>A transistor comprises a nanowire (22, 22') having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).</p> |
申请公布号 |
WO2007086009(A1) |
申请公布日期 |
2007.08.02 |
申请号 |
WO2007IB50241 |
申请日期 |
2007.01.24 |
申请人 |
NXP B.V.;HURKX, FRED;AGARWAL, PRABHAT |
发明人 |
HURKX, FRED;AGARWAL, PRABHAT |
分类号 |
H01L29/06;H01L21/336;H01L29/10;H01L29/78 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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