| 摘要 |
Source voltage and substrate voltage are supplied to a semiconductor integrated circuit 1 E from the regulator circuits 11 C and 21 C of a power supply circuit 1 C via a power detection compensating circuit 1 D. The power efficiency value of a regulator is stored in the resistor 13 D, various detection information and power values are input to an operator 14 D, the power values and the power efficiency values of the regulator circuits 11 C and 21 C are accumulated, and the power sum of a semiconductor integrated circuit 1 E and a power supply circuit 1 C are output. Minimum power implementation information corresponding to the various detection information of the semiconductor integrated circuit 1 E is stored in an LUT 15 D. Variable resistances R 1 a and R 2 a are controlled for determining the reference voltage values of the regulator circuits 11 C and 21 C so that the power sum is the minimum power value by comparing the minimum power implementation information with the output of the operator 14 D.
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