发明名称 Chip design verification apparatus and method
摘要 Chip design verification apparatus and method. The method of verifying the chip design includes a software side operation step of transmitting output data generated by the operation of the software block to the interface means, determining whether the output data of the hardware block received via the interface means is valid by executing the chip design verification program, and applying only the valid output data of the hardware block to the software block; and a hardware side operation step of transmitting output data generated by the operation of the hardware block to the software block, determining whether the output data of the software block received is valid by executing the chip design verification program in the interface means, and applying only the valid output data of the software block to the hardware block. Accordingly, chip design errors may be detected when the chip is designed and a faster chip design verification speed may be obtained.
申请公布号 US2007180413(A1) 申请公布日期 2007.08.02
申请号 US20050589595 申请日期 2005.02.17
申请人 PARK HYUN-JU 发明人 PARK HYUN-JU
分类号 G06F17/50;G06F11/22;G06F11/273 主分类号 G06F17/50
代理机构 代理人
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