<p>In each of the first to m-th columns in the structure of a pixel part (10), a plurality of pixel signals outputted from a plurality of pixels arranged in the column direction are outputted to the respective ones of a plurality of different output signal lines (151-15n). Then, the reading and resetting controls of the plurality of pixels are implemented at the same time.</p>
申请公布号
WO2007086175(A1)
申请公布日期
2007.08.02
申请号
WO2006JP321116
申请日期
2006.10.24
申请人
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;SOWA, TAKESHI;HARA, KUNIHIKO;INAGAKI, MAKOTO;MATSUNAGA, YOSHIYUKI