发明名称 System bus control apparatus, integrated circuit and data processing system
摘要 The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer. A system bus control apparatus includes a system bus that is a path of data transferred from a bus master, a bus condition monitoring section that monitors a used condition or unused condition of the system bus, a bus allocating section that allocates a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request, and a bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width. Accordingly, the bus width of the data to be transferred is changed in accordance with the bus width permitted to be used, whereby the transfer request is not brought into a stand-by condition.
申请公布号 US2007180179(A1) 申请公布日期 2007.08.02
申请号 US20070651005 申请日期 2007.01.09
申请人 SHARP KABUSHIKI KAISHA 发明人 IRISA NAOKI
分类号 G06F13/40 主分类号 G06F13/40
代理机构 代理人
主权项
地址