| 发明名称 |
Apparatus and method of equalisation |
| 摘要 |
<p>To reduce the number of components needed when compared with an exact-calculation analog equalizer, an analog equalizer includes an iterative mechanism arranged in operation to generate an estimate of marginal posterior expectations for received bit values.</p> |
| 申请公布号 |
GB2425236(B) |
申请公布日期 |
2007.08.01 |
| 申请号 |
GB20050007375 |
申请日期 |
2005.04.12 |
| 申请人 |
TOSHIBA RESEARCH EUROPE LIMITED |
发明人 |
ROBERT JAN PIECHOCKI;JOSEP VICENT SOLER GARRIDO |
| 分类号 |
H04H20/88;H04L25/03;H04B3/06;H04J99/00 |
主分类号 |
H04H20/88 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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