TAPE PACKAGE WITH MULTY LAYER TAPE SUBSTRATE

摘要

A tape package having a multi-layered wiring substrate is provided to increase the number of pins of a semiconductor chip and density of a line pattern by electrically connecting the semiconductor chip with a large number of pins with use of a tape wiring substrate including a plurality of line pattern layers. A tape wiring substrate(130) includes a plurality of line pattern layers(132a,132b) formed between a plurality of insulating layers(134a,134b), and a chip mounting area(140) formed as a stepped groove on an upper surface thereof. Leads(132c,132d) formed at ends of the respective line pattern layers are exposed to the outside through the groove in the chip mounting area. A semiconductor chip(120) includes contact portions formed in a plurality of rows having different lengths, and the contact portions of the respective rows contact the leads of the respective line pattern layers in the chip mounting area.